Boosting Reads of Chunks of Data

ABSTRACT

Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.

BACKGROUND Field of the Disclosure

Embodiments of the present disclosure generally relate to reading datausing host performance booster (HPB).

Description of the Related Art

Sequential access to a data file means that the computer system reads orwrites information to the file sequentially, starting from the beginningof the file and proceeding step by step. Random access, on the otherhand, means that the computer system can read or write informationanywhere in the data file. In typical scenarios, about fifty percent ofthe reads are of a size 4K, but in many cases, random data of 8K-128K isread.

Flash management for translating the logical address of the data to thephysical address on the flash is stored in tables saved in the flashtranslation layer (FTL). Flash management is typically performed at thegranularity of 4K data units. The FTL tables are stored in a specialarea of the flash memory. A small cache is often kept in RAM on the datastorage device to improve the random read performance. Storing the smallcache necessitates a performance tradeoff on the random range supported.The larger the range, the more RAM that is needed. In cost sensitivedevices, the random range is typically limited.

To factor this problem differently, the UFS (Universal Flash Storage)community has been working on methods to improve the random readperformance by moving the cache to host memory. A large DRAM in the hostdevice is more cost efficient than in the data storage device SRAM. Toimplement the DRAM cache, the HPB protocol has been defined. In the HPBapproach, each 4K logical address has an associated 8B entry thatprovides the physical block address (PBA) on the media in a deviceproprietary format.

The data storage device is responsible for providing the 8 byte HPBentry for each 4K data unit. The host is then responsible for providingthis 8 byte entry as part of the data read command. A limitation of thisapproach is that the approach only optimizes reads of 4K. Since a goodpercentage of random reads are greater than 4K, there is still room forimprovement.

Therefore, there is a need in the art for an improved read using HPB.

SUMMARY

The present disclosure generally relates to using an encoded HPB entryin a read command to provide the PBA as well as the run length. The LBA(Logical Block Address), PBA, and run length are placed in an HPB readbuffer table. The HPB read buffer table is located in the host device.When the read command is received by the data storage device, the datastorage device will read the LBA, transfer length, and HPB entry fromthe read command. The HPB entry will contain the PBA for the LBA as wellas the run length for the data that was written in flash. For reads ofdata that may not have been written sequentially, the HPB will containthe LBA, transfer length, and references to entries in a write buffertable that is stored in the data storage device.

In one embodiment, a data storage device comprises a memory device and acontroller coupled to the memory device, where the controller isconfigured to create a host performance booster (HPB) read buffer table.The HPB table includes logical block addresses (LBAs), physical blockaddresses (PBAs), and run lengths for the PBAs, and deliver the HPB readbuffer table to a host device.

In another embodiment, a data storage device comprises a memory deviceand a controller coupled to the memory device. The controller isconfigured to receive a host performance booster (HPB) read command,wherein the HPB command includes a run length that is not encrypted,review encoded information from HPB command, retrieve requested data,and deliver the requested data to a host device.

In another embodiment, a data storage device comprises a memory device,a controller coupled to the memory device, and means to create a hostperformance booster (HPB) read buffer table, where the HPB read buffertable includes a table of the 8-byte HPB entries, one per LBA.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 is a schematic block diagram illustrating a storage system havinga storage device that may function as a storage device for a hostdevice, in accordance with one or more techniques of this disclosure.

FIG. 2 is a flow chart illustrating a method of forming an HPB readbuffer according to one embodiment.

FIG. 3A is a schematic illustration of a HPB read buffer table accordingto one embodiment.

FIG. 3B is a schematic illustration of a HPB read buffer table accordingto another embodiment.

FIG. 4 is a flow chart illustrating a method of forming a HPB writebuffer according to one embodiment.

FIG. 5 is a schematic illustration of a HPB read command according toone embodiment.

FIG. 6 is flow chart illustrating a method of processing a read commandaccording to one embodiment.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in oneembodiment may be beneficially utilized on other embodiments withoutspecific recitation.

DETAILED DESCRIPTION

In the following, reference is made to embodiments of the disclosure.However, it should be understood that the disclosure is not limited tospecific described embodiments. Instead, any combination of thefollowing features and elements, whether related to differentembodiments or not, is contemplated to implement and practice thedisclosure. Furthermore, although embodiments of the disclosure mayachieve advantages over other possible solutions and/or over the priorart, whether or not a particular advantage is achieved by a givenembodiment is not limiting of the disclosure. Thus, the followingaspects, features, embodiments and advantages are merely illustrativeand are not considered elements or limitations of the appended claimsexcept where explicitly recited in a claim(s). Likewise, reference to“the disclosure” shall not be construed as a generalization of anyinventive subject matter disclosed herein and shall not be considered tobe an element or limitation of the appended claims except whereexplicitly recited in a claim(s).

The present disclosure generally relates to using an encoded HPB entryin a read command to provide the PBA as well as the run length. The LBA,PBA, and run length are placed in an HPB read buffer table. The HPB readbuffer table is I in the host device. When the read command is receivedby the data storage device, the data storage device will read the LBA,transfer length, and HPB entry from the read command. The HPB entry willcontain the PBA for the LBA as well as the run length for the data to beread. For non-sequential reads, the HPB entry sent with the command willcontain references to one to eight entries in the HPB read buffer tableaccording to the transfer length. The write buffer table is stored inthe data storage device after specific write buffer commands.

FIG. 1 is a schematic block diagram illustrating a storage system 100 inwhich data storage device 106 may function as a storage device for ahost device 104, in accordance with one or more techniques of thisdisclosure. For instance, the host device 104 may utilize NVM 110included in data storage device 106 to store and retrieve data. The hostdevice 104 comprises a host DRAM 138 that comprises a read buffer 140.The read buffer 140 may be used to store read commands to be sent to thedata storage device 106 and may be utilized with a host performancebooster (HPB) protocol. In some examples, the storage system 100 mayinclude a plurality of storage devices, such as the data storage device106, which may operate as a storage array. For instance, the storagesystem 100 may include a plurality of data storage devices 106configured as a redundant array of inexpensive/independent disks (RAID)that collectively function as a mass storage device for the host device104.

The storage system 100 includes a host device 104 which may store and/orretrieve data to and/or from one or more storage devices, such as thedata storage device 106. As illustrated in FIG. 1, the host device 104may communicate with the data storage device 106 via an interface 114.The host device 104 may comprise any of a wide range of devices,including computer servers, network attached storage (NAS) units,desktop computers, notebook (i.e., laptop) computers, tablet computers,set-top boxes, telephone handsets such as so-called “smart” phones,so-called “smart” pads, televisions, cameras, display devices, digitalmedia players, video gaming consoles, video streaming device, and thelike.

The data storage device 106 includes a controller 108, non-volatilememory 110 (NVM 110), a power supply 111, volatile memory 112, aninterface 114, and a write buffer 116. The controller 108 comprises ahost performance booster (HPB) element 118. In one embodiment, the HPBelement 118 is firmware that utilizes a HPB protocol to optimize readsin the data storage device 106. In another embodiment, the HPB element118 is a hardware component of the controller 108. In some examples, thedata storage device 106 may include additional components not shown inFIG. 1 for sake of clarity. For example, the data storage device 106 mayinclude a printed board (PB) to which components of the data storagedevice 106 are mechanically attached and which includes electricallyconductive traces that electrically interconnect components of the datastorage device 106, or the like. In some examples, the physicaldimensions and connector configurations of the data storage device 106may conform to one or more standard form factors. Some example standardform factors include, but are not limited to, 3.5″ data storage device(e.g., an HDD or SSD), 2.5″ data storage device, 1.8″ data storagedevice, peripheral component interconnect (PCI), PCI-extended (PCI-X),PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI,etc.). In some examples, the data storage device 106 may be directlycoupled (e.g., directly soldered) to a motherboard of the host device104. It is to be understood that while the description herein is madewith reference to embedded flash devices that are in compliance with UFSprotocol, it is contemplate that the embodiments discussed herein may beapplicable to other standards as well, such as PCIe.

The interface 114 of the data storage device 106 may include one or bothof a data bus for exchanging data with the host device 104 and a controlbus for exchanging commands with the host device 104. The interface 114may operate in accordance with any suitable protocol. For example, theinterface 114 may operate in accordance with one or more of thefollowing protocols: advanced technology attachment (ATA) (e.g.,serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol(FCP), small computer system interface (SCSI), serially attached SCSI(SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI,GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD(OCSSD), or the like. It is to be understood that while the descriptionherein is made with reference to HPB protocol for UFS devices that areintended for embedded flash memory, it is contemplate that theembodiments discussed herein may be applicable to other protocols aswell, such as SCSI. The electrical connection of the interface 114(e.g., the data bus, the control bus, or both) is electrically connectedto the controller 108, providing electrical connection between the hostdevice 104 and the controller 108, allowing data to be exchanged betweenthe host device 104 and the controller 108. In some examples, theelectrical connection of the interface 114 may also permit the datastorage device 106 to receive power from the host device 104. Forexample, as illustrated in FIG. 1, the power supply 111 may receivepower from the host device 104 via the interface 114.

The data storage device 106 includes NVM 110, which may include aplurality of memory devices or memory units. NVM 110 may be configuredto store and/or retrieve data. For instance, a memory unit of NVM 110may receive data and a message from the controller 108 that instructsthe memory unit to store the data. Similarly, the memory unit of NVM 110may receive a message from the controller 108 that instructs the memoryunit to retrieve data. In some examples, each of the memory units may bereferred to as a die. In some examples, a single physical chip mayinclude a plurality of dies (i.e., a plurality of memory units). In someexamples, each memory unit may be configured to store relatively largeamounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB,16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

In some examples, each memory unit of NVM 110 may include any type ofnon-volatile memory devices, such as flash memory devices, phase-changememory (PCM) devices, resistive random-access memory (ReRAM) devices,magnetoresistive random-access memory (MRAM) devices, ferroelectricrandom-access memory (F-RAM), holographic memory devices, and any othertype of non-volatile memory devices.

The NVM 110 may comprise a plurality of flash memory devices or memoryunits. Flash memory devices may include NAND or NOR based flash memorydevices, and may store data based on a charge contained in a floatinggate of a transistor for each flash memory cell. In NAND flash memorydevices, the flash memory device may be divided into a plurality ofblocks which may be divided into a plurality of pages. Each block of theplurality of blocks within a particular memory device may include aplurality of NAND cells. Rows of NAND cells may be electricallyconnected using a word line to define a page of a plurality of pages.Respective cells in each of the plurality of pages may be electricallyconnected to respective bit lines. Furthermore, NAND flash memorydevices may be 2D or 3D devices, and may be single level cell (SLC),multi-level cell (MLC), triple level cell (TLC), or quad level cell(QLC). The controller 108 may write data to and read data from NANDflash memory devices at the page level and erase data from NAND flashmemory devices at the block level.

The data storage device 106 includes a power supply 111, which mayprovide power to one or more components of the data storage device 106.When operating in a standard mode, the power supply 111 may providepower to the one or more components using power provided by an externaldevice, such as the host device 104. For instance, the power supply 111may provide power to the one or more components using power receivedfrom the host device 104 via the interface 114. In some examples, thepower supply 111 may include one or more power storage componentsconfigured to provide power to the one or more components when operatingin a shutdown mode, such as where power ceases to be received from theexternal device. In this way, the power supply 111 may function as anonboard backup power source. Some examples of the one or more powerstorage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount ofpower that may be stored by the one or more power storage components maybe a function of the cost and/or the size (e.g., area/volume) of the oneor more power storage components. In other words, as the amount of powerstored by the one or more power storage components increases, the costand/or the size of the one or more power storage components alsoincreases.

The data storage device 106 also includes volatile memory 112, which maybe used by controller 108 to store information. Volatile memory 112 maybe comprised of one or more volatile memory devices. In some examples,the controller 108 may use volatile memory 112 as a cache. For instance,the controller 108 may store cached information in volatile memory 112until cached information is written to non-volatile memory 110. Asillustrated in FIG. 1, volatile memory 112 may consume power receivedfrom the power supply 111. Examples of volatile memory 112 include, butare not limited to, random-access memory (RAM), dynamic random accessmemory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM(e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)).

The data storage device 106 includes a controller 108, which may manageone or more operations of the data storage device 106. For instance, thecontroller 108 may manage the reading of data from and/or the writing ofdata to the NVM 110. In some embodiments, when the data storage device106 receives a write command from the host device 104, the controller108 may initiate a data storage command to store data to the NVM 110 andmonitor the progress of the data storage command. The controller 108 maydetermine at least one operational characteristic of the storage system100 and store the at least one operational characteristic to the NVM110. In some embodiments, when the data storage device 106 receives awrite command from the host device 104, the controller 108 temporarilystores the data associated with the write command in the internal memoryor write buffer 116 before sending the data to the NVM 110.

FIG. 2 is a flow chart illustrating a method of forming a HPB readbuffer according to one embodiment. The HPB read buffer may be the readbuffer 140 of the host device 104 of FIG. 1. The HPB read buffer is asection of DRAM in a host device 104 that stores information, such asLBAs, PBA, and run length for data to be read. The HPB read buffer is acache of an L2P map data of the logical block addresses (LBAs) of theNVM, such as the NVM 110 of FIG. 1, of the storage device, such as thedata storage device 106 of FIG. 1. The volatile memory, such as thevolatile memory 112 of FIG. 1, of a data storage device 106 is limitedin capacity. Because of the storage capacity limitation, the L2P map ofthe data storage device 106 may not include the entire L2P information.However, the host DRAM, such as the host DRAM 138 of FIG. 1, has alarger capacity than that of the volatile memory 112 of the data storagedevice 106. The host DRAM 138 may store a complete L2P map of the LBAsstored in the NVM 110 of the data storage device 106 in the read buffer140.

A write command is received by the controller, such as the controller108 of FIG. 1, and is written sequentially to an available location inthe NVM 110 at block 202. The location of the data corresponding to thewrite command is stored as a LBA in a L2P table of the volatile memory112 of the data storage device 106. The controller 108 utilizes a HPBelement 118 to create a correspondence between the LBA and the physicalblock address (PBA) at block 204. The PBA is the physical location ofthe data in the NVM 110, whereas the LBA is the logical location of thedata in the NVM 110. The HPB element 118 calculates a run length (RL)for the host for each LBA and PBA correspondence. The run length isdetermined by the number of sequential data locations in the NVM 110.For example, if 6 LBAs (i.e., LBA0-LBA5) are sequential, LBA0 isassociated with a RL of 6, LBA1 is associated with a RL of 5, andso-forth, where the last LBA, LBA5, associated with a RL of 1. The data(i.e., RL information) is released to the host HPB read buffer 140 atblock 208. In one embodiment, the read buffer command is limited toabout 32K.

FIG. 3A and FIG. 3B are schematic illustrations of a HPB read buffertable according to various embodiments. The HPB read buffer table may bestored in the read buffer 140 of the host DRAM 138 of FIG. 1. The HPBread buffer table comprises the LBA and PBA correspondence created inmethod 200 as well as the run length for each LBA and PBA correspondencecalculated in method 200. The HPB table may have a maximum run length ofabout 16, of about 32, of about 64, of about 128, or about 256. The runlength size may be a multiple of 4K size. The previous values for runlength are not intended to be limiting, but to provide examples ofpossible embodiments. Furthermore, the HPB read buffer for each entry,such as LBA1, PBA X, and RL 8 of FIG. 3A corresponds to the LBA and HPBentry of the HPB read command.

FIG. 3A is a schematic illustration of a HPB read buffer table accordingto one embodiment. The run length of the HPB read buffer table iscalculated counting forward. For example, a first LBA1 corresponds witha PBA X, while a second LBA2 corresponds with a PBA X+1, and so-forth.Each time the HPB element 118 of the controller 108 of FIG. 1 advancesto the next LBA/PBA combination to determine a run length, the HPBelement 118 reads each entry prior. For example, in order to read LBA3associated with X+2, LBA1 associated with X and LBA2 associated with X+1are read. However, LBA1 associated with X and LBA2 associated with X+1have already been read during a previous pass through. When the HPBelement 118 recognizes that a non-consecutive LBA/PBA combination is inthe list, the PBA entry resets so that a non-consecutive LBA9 refers toa PBA Y.

FIG. 3B is a schematic illustration of a HPB read buffer table accordingto another embodiment. The run length of the HPB read buffer table iscalculated counting backwards. For example, a last LBA8 corresponds witha PBA X, while a second to last LBA2 corresponds with a PBA X−1, andso-forth. Unlike calculating counting forwards as referenced in FIG. 3A,counting backwards may not require repetitive reads to determine a runlength. The DMA engine may enable the backwards run. For example, sincethe HPB element 118 of the controller 108 recognizes that the last LBA,such as LBA8 of FIG. 3B, is the last consecutive LBA in the table, theHPB element 118 utilizes logic to determine if the previous LBA in thetable, such as the second to last LBA7, is equal to the current LBAminus 1. When the HPB element 118 recognizes that a non-consecutiveLBA/PBA combination is in the list, the PBA entry resets so that anon-consecutive LBA9 refers to a PBA Y.

FIG. 4 is a flow chart illustrating a method of forming a HPB writebuffer according to one embodiment. The HPB write buffer may be thewrite buffer 116 of FIG. 1. A write buffer command is received from thehost, such as the host device 104 of FIG. 1, at block 402. The writebuffer command is associated with a portion of the HPB read buffer tablethat is relevant for non-consecutive reads. The write buffer commandreferences the relevant HPB entry. The write buffer may be 2K byteswhich is equal to about 256 entries of 8 bytes each. The write bufferreferences a portion of the read buffer table by the ID. If the readbuffer is 8 bytes and each byte refers to 1 of the 256 entries of thewrite buffer, then each read buffer may contain up to 8 write bufferentries. Furthermore, the write buffer table is written to the writebuffer 116 of a data storage device, such as the data storage device 106of FIG. 1, at block 404.

FIG. 5 is a schematic illustration of a HPB read command according toone embodiment. The HPB read command is stored in a host read buffer,such as the read buffer 140 of the host DRAM of the host device 104 ofFIG. 1. The HPB read command comprises of the following three parts: theLBA 502, the HPB entry 504, and the transfer length 506. The HPB readcommand is 16 bytes.

The LBA 502 is a 4 byte entry that corresponds to a relevant PBA ofdata. The LBA 502 signifies the location of where data is stored in thememory device. In one embodiment, the HPB entry is comprised of the PBAand the RL of the LBA/PBA correspondence. In another embodiment, the HPBentry comprises a pointer or direction to an HPB write buffer table. TheHPB entry size is fixed and is about 8 bytes. Furthermore, if data ismoved in the flash memory, the data will be moved in a group so that theorder of the data remains sequential. However, if the data is not movedsequentially, the HPB read buffer table is updated and sent to the host.Anytime the data sequence is changed in the NVM, the host read buffer isupdated with the updated HPB read buffer tables corresponding to thechanged data sequence. The final 4 bytes of the HPB read command isassociated with the transfer length 506 of the PBA. The transfer length506 corresponds with the run length of the HPB read buffer. If thetransfer length 506 is greater than the run length, then a standardflash read occurs. However, if the run length is equal to or greaterthan the transfer length 506, the data is read from the memory deviceusing the HPB protocol without checking a flash translation layer (FTL)table. The size of the run length up to 256K bytes. The size listed isnot intended to be limiting, but to provide an example of a possibleembodiment.

For example, the HPB read command may be for LBA4 associated with a PBAX+3 as shown in FIG. 3A. If the transfer length 506 associated with theHPB read command is 5, then the host device, such as the host device 104of FIG. 1, is able to read the LBA4 directly from the NVM by utilizingthe appropriate HPB protocol without checking the FTL table. However, ifthe transfer length 506 associated with the HPB read command is 6, thenthe host device is unable to read directly from the NVM utilizing theHPB protocol. The data associated with LBA4 will be read utilizing thestandard read protocol. Furthermore, the run length is visible to thehost. Because the run length is visible to the host, the host may splitup HPB read commands so that device may avoid doing a standard read andhaving to reference the FTL table.

FIG. 6 is a flow chart illustrating a method 600 of processing a readcommand according to one embodiment. The host device may be the hostdevice 104 of FIG. 1. The HPB read buffer table may be the read buffer140 of the host DRAM 138 of the host device 104 of FIG. 1. The writebuffer table may be the write buffer 116 coupled to the HPB element 118of the controller 108 of the data storage device 106 of FIG. 1. At block602, the controller 108 receives a read command from the host device104. The controller determines if the read command is for sequentialread at block 604.

If the read command received is for a sequential read at block 604, thenthe HPB entry of the read command is read at block 606. The HPB entryrefers to the PBA and the run length of the associated LBA. Furthermore,if the transfer length does not satisfy the run length requirement ofthe HPB read command, the standard read protocol may occur. However, ifthe transfer length does satisfy the run length requirement, then thedata is retrieved from the data location at block 612 without accessingthe FTL table.

However, if the read command is not for a sequential read (i.e., arandom, non-consecutive read) at block 604, then the HPB entry of theread command is read at block 608. The controller checks the writebuffer table at 610 to request the relevant HPB read buffer table. Thedata is retrieved from the data location at block 612.

By encoding the HPB entry of the read command with the PBA and runlength, sequential reads can be more efficient. By encoding the HPBentry of the read command with a reference to a HPB write buffer,non-sequential reads can be more efficient.

In one embodiment, a data storage device comprises: a memory device; anda controller coupled to the memory device, wherein the controller isconfigured to: create a host performance booster (HPB) read buffertable, wherein the HPB table includes logical block addresses (LBAs),physical block addresses (PBAs), and run lengths for the PBAs; anddeliver the HPB read buffer table to a host device. The controller isfurther configured to receive a HPB read command, wherein the HPB readcommand includes an LBA, a transfer length, and an HPB entry. The HPBentry includes the PBA for the LBA and the run length for the PBA. TheHPB entry includes coherency information. The controller is furtherconfigured to read the data from the memory device using the HPB entrywithout checking a flash translation layer (FTL) table. The controlleris further configured to receive a write buffer command table and storethe write buffer command table in the memory device. The controller isfurther configured to receive a HPB read command, wherein the HPB readcommand includes an LBA, a transfer length, and an HPB entry, andwherein the HPB entry references a location in the write buffer commandtable. The HPB entry is encrypted, and wherein the run length is notencrypted.

In another embodiment, a data storage device comprises: a memory device;and a controller coupled to the memory device, wherein the controller isconfigured to: receive a host performance booster (HPB) read command,wherein the HPB command includes a run length that is not encrypted;review encoded information from HPB command; retrieve requested data;and deliver the requested data to a host device. The encoded informationincludes a physical block address (PBA). The run length is greater than4K. The encoded information references an HPB write buffer table. TheHPB write buffer table is disposed in the data storage device. Thecontroller is further configured to create a HPB read buffer table.

In another embodiment, a data storage device comprises: a memory device;a controller coupled to the memory device; and means to create a hostperformance booster (HPB) read buffer table, wherein the HPB read buffertable includes logical block address (LBA) information, physical blockaddress (PBA) information, and run length. The data storage devicefurther comprises: means to receive a HPB read command; and means toreceive an HPB write command buffer table. The HPB read command containsan LBA, a transfer length, and an HPB entry. The HPB entry contains aPBA and a run length. The HPB entry contains a reference to the HPBwrite command buffer table. The data storage device further comprisesmeans to calculate a run length for a PBA entry.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A data storage device, comprising: a memorydevice; and a controller coupled to the memory device, wherein thecontroller is configured to: create a host performance booster (HPB)read buffer table, wherein the HPB table includes logical blockaddresses (LBAs), physical block addresses (PBAs), and run lengths forthe PBAs; and deliver the HPB read buffer table to a host device.
 2. Thedata storage device of claim 1, wherein the controller is furtherconfigured to receive a HPB read command, wherein the HPB read commandincludes an LBA, a transfer length, and an HPB entry.
 3. The datastorage device of claim 2, wherein the HPB entry includes the PBA forthe LBA and the run length for the PBA.
 4. The data storage device ofclaim 3, wherein the HPB entry includes coherency information.
 5. Thedata storage device of claim 2, wherein the controller is furtherconfigured to read the data from the memory device using the HPB entrywithout checking a flash translation layer (FTL) table.
 6. The datastorage device of claim 1, wherein the controller is further configuredto receive a write buffer command table and store the write buffercommand table in the memory device.
 7. The data storage device of claim6, wherein the controller is further configured to receive a HPB readcommand, wherein the HPB read command includes an LBA, a transferlength, and an HPB entry, and wherein the HPB entry references alocation in the write buffer command table.
 8. The data storage deviceof claim 7, wherein the HPB entry is encrypted, and wherein the runlength is not encrypted.
 9. A data storage device, comprising: a memorydevice; and a controller coupled to the memory device, wherein thecontroller is configured to: receive a host performance booster (HPB)read command, wherein the HPB command includes a run length that is notencrypted; review encoded information from HPB command; retrieverequested data; and deliver the requested data to a host device.
 10. Thedata storage device of claim 9, wherein the encoded information includesa physical block address (PBA).
 11. The data storage device of claim 10,wherein the run length is greater than 4K.
 12. The data storage deviceof claim 9, wherein the encoded information references one or more HPBwrite buffer tables.
 13. The data storage device of claim 12, whereinthe HPB write buffer table is disposed in the data storage device. 14.The data storage device of claim 9, wherein the controller is furtherconfigured to create a HPB read buffer table.
 15. A data storage device,comprising: a memory device; a controller coupled to the memory device;and means to create a host performance booster (HPB) read buffer table,wherein the HPB read buffer table includes logical block address (LBA)information, physical block address (PBA) information, and run length.16. The data storage device of claim 15, further comprising: means toreceive a HPB read command; and means to receive an HPB write commandbuffer table.
 17. The data storage device of claim 16, wherein the HPBread command contains an LBA, a transfer length, and an HPB entry. 18.The data storage device of claim 17, wherein the HPB entry contains aPBA and a run length.
 19. The data storage device of claim 17, whereinthe HPB entry contains a reference to the HPB write command buffertable.
 20. The data storage device of claim 15, further comprising meansto calculate a run length for a PBA entry.